PC Elektro 3/PC-Elektro-3-cd1.bin/DesignWorks Professional Schematic Capture/DesignWorks4Setup.exe/Main/VHDL.RFM

Text File | 2004-10-16 | 3.9 KB | 93 lines

{
  VHDL report form for DesignWorks.
  c 1995
  by Capilano Computing Systems Ltd.
}
$CHECK("Design must be in hierarchy pure mode") $FLAT $PHYSICAL
$NOTES
Attribute Fields Used:
VType    - Define local signal and port types (bit, bit_vector.).
VGenericDecl - Define body of generic declarations for components
VGenericInst - Define body of generic declaration of instances
All pins on symbols and all local signals must have VType.
All unconnected pins are assigned "open" signals.
Signals can be labeled with "0", "1", open or aggregates and
not have VType. I borrowed open emitter pin type for the "buffer" attribute

Descriptions are placed with each component and entity as comments.
 (for unconnected pins)

*** IMPORTANT NOTE ***

This netlist script is provided with DesignWorks on an "as is" basis with no guarantee that it will work in any particular environment.  Capilano Computing has no control over the file formats that may be used by these systems.  These scripts have generally been created and tested in conjunction with DesignWorks users and were developed for use with a specific version of the target system.  The third party developer may change formats at any time, and we do not have the resources to track every version of every system on the market.

If this script does not appear to generate the format required for your system, we are happy to assist customers in generating the appropriate format.  Please contact us at [e-mail] and provide a sample netlist and as much information as you can about the required format.
$END
$CREATEREPORT($DESIGNNAME.vhd) $PROMPT $CREATOR(ttxt)
$HIERARCHY $PURE
$FIND $SIGNALS $NUMPINS(2) $NOT $SIGNAME
$CHECK(Signal names missing - Default names will be assigned if continued) $SIGNALS
$ASSIGNNAMES $SIGNALS $FORMAT(S0)
$COLUMNS(32000)
$ROWS(32000)
------------------------------------------------------------------------
-- File: $DESIGNNAME.vhd
$FIND $DEVICES &Depth
$SORT $DEVICES &Depth $TYPENAME
$COMBDEVSON
$DEVICES-- entity $TYPENAME
-- VHDL generated by DesignWorks
-- &Designer
-- $DATE $TIME
------------------------------------------------------------------------
{ The following $DEFINECIRCUIT section defines the text to be output
  for each internal circuit. }
$DEFINECIRCUIT
$PINTYPEFORMAT in out out inout out out out out out out in out in out in buffer out
$FIND $SIGNALS
{ List components in an architecture }
$FIND $DEVICES &VGenericDecl
$SORT $DEVICES $TYPENAME
$COMBDEVSON
$CONTSTART(            )
$CONTEND(;)
$MAXITEMSPERLINE(1)
$ITEMSEPARATOR(;)
$DEVPINFORMAT$PINNAME: $PINTYPE &VType
$DEVICES    -- &Description$NEWLINE    component $TYPENAME is$NEWLINE        generic(&VGenericDecl);$NEWLINE        port($NEWLINE            $PINS);$NEWLINE    end component;
$FIND $DEVICES $NOT &VGenericDecl
$SORT $DEVICES $TYPENAME
$COMBDEVSON
$DEVICES    -- &Description$NEWLINE    component $TYPENAME is$NEWLINE        port($NEWLINE            $PINS);$NEWLINE    end component;
{ List local signals in an architecture }
$FIND $SIGNALS &VType
$SORT $SIGNALS &VType
$SIGNALS    signal $SIGNAME: &VType;
{ List body of architecture & instances of components }
begin
$FIND $SIGNALS
$UNNAMEDSIGS(open)
$FIND $DEVICES &VGenericInst
$SORT $DEVICES $TYPENAME
$COMBDEVSOFF
$MAXITEMSPERLINE(255)
$ITEMSEPARATOR(, )
$DEVPINFORMAT$PINNAME=>$SIGNAME
$DEVICES    $DEVNAME: $TYPENAME generic map(&VGenericInst) port map($PINS);
$FIND $DEVICES $NOT &VGenericInst
$SORT $DEVICES $TYPENAME
$DEVICES    $DEVNAME: $TYPENAME port map($PINS);
$END
{ List entity and port list of each item in list }
$FIND $SIGNALS
$FIND $DEVICES &Depth
$SORT $DEVICES &Depth $TYPENAME
$COMBDEVSON
$PINTYPEFORMAT in out out inout out out out out out out in out in out in buffer out
$CONTSTART(        )
$CONTEND(;)
$ITEMSEPARATOR(;$NEWLINE)
$DEVPINFORMAT$PINNAME: $PINTYPE &VType
$DEVICES--&Description$NEWLINEentity $TYPENAME is$NEWLINE    port($NEWLINE$MAXITEMSPERLINE(1)        $PINS);$NEWLINEend $TYPENAME;$NEWLINE$NEWLINEarchitecture STRUCTURED of $TYPENAME is$NEWLINE$INTERNALend STRUCTURED;$NEWLINE